One time programmable (OTP) and multi-time programmable (MTP) memories have been recently introduced for beneficial use in a number of applications where customization is required for both digital and analog designs. These applications include data encryption, reference trimming, manufacturing identification (ID), security ID, and many other applications. Incorporating OTP and MTP memories nonetheless typically comes at the expense of some additional processing steps.
For example, OTP and MTP memories may include flash memory devices that store data on an array of programmable memory cells. Typically, these cells are made from floating-gate metal oxide semiconductor field effect transistors (MOSFETs) that can be electrically erased and reprogrammed. PRIOR ART FIG. 1 illustrates a non-volatile floating gate MOSFET that is configured to store an electrical charge for extended periods of time without the presence of a power supply. The MOSFET 100 is shown as a planar structure where features are placed on the surface of a silicon wafer or substrate 110. As shown, the floating gate MOSFET includes a p-type substrate 110, a drain region 120 with n-type dopants, and a source region 125 with n-type dopants. A gate structure is disposed on top of the substrate, and includes a floating gate 150 that is isolated by the oxide layers 140 and 160. Because the floating gate 150 is electrically isolated, any electrons placed in this layer are trapped, and will remain trapped under normal conditions for many years. A control gate is also deposited over the floating gate 150 with an oxide layer 140 interposed therebetween. The control gate 130 is capacitively coupled to the floating gate 150 and is used to control the operation of the MOSFET 100.
Programming, erasing, and reading the MOSFET 100 is achieved by applying various voltages between the control gate, source region, and drain region in different combinations. For flash memory, these voltages are comparatively high, such as up to and exceeding 12 volts. For instance, when the MOSFET 100 is programmed, an n-type channel 115 is formed between the drain region 120 and source region 125. During programming, electrons are injected through oxide 160, and subsequently trapped in the floating gate 150. When reading a programmed MOSFET 100, current does not flow through MOSFET 100, which indicates a logic-0. On the other hand, an erased MOSFET 100 does not have electrons present on the floating gate 150. As such, when reading an erased MOSFET 100, current flows through MOSFET 100, which indicates a logic-1.
Numerous steps are implemented to fabricate one or more MOSFETs 100 on a silicon wafer. These include various deposition, removal, patterning, and masking steps to grow the features of the MOSFET 100, including the drain and source regions, the floating gate oxide layer, and the control gate oxide layer. For a typical flash memory cell having a double polysilicon gate structure, it may take up to 20 masking steps. Each subsequent masking step will increase the fabrication cost and also degrade the quality of the transistors. As such, for embedded applications, the use of flash memory fabricated onto portions of the silicon chip may be too costly for the function provided, and may affect the quality of all the active transistors on the chip.
An effort has been made to planarize the memory cell by moving the control gate to the side of the active memory transistor. More particularly, the control gate includes an n-well built to the side that is capacitively coupled to the floating gate of the memory device. In some cases, the n-well is coupled to the drain of the device. Since the n-well is capacitively coupled to the floating gate, voltages applied to the drain will, in part, also be applied to the gate, effectively creating a two-terminal memory device. While this structure reduces the cost of fabricating the embedded memory chip, as it does not require double polysilicon gate layers, a disadvantage is that additional planar real estate on the surface of the chip is needed to build the control gate to the side of the active memory device.
As computing devices increasingly become more functionally complex, their dimensions are also becoming thinner and smaller, such as, in the case of hand-held devices. As a result, planar real estate on chips used within the device is at a premium. It would be advantageous to have memory devices that do not require additional masking steps for fabricating double polysilicon gate layers, while at the same time reduces the planar footprint of the memory device.